1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor which can be used as an element of an electric switch for electric power.
2. Description of the Related Arts
There have been many reports recently related to an insulated gate bipolar transistor used as a switching element for electric power. This element, while having a configuration similar to a power MOSFET, achieves coexistence of a high withstand voltage and a low ON resistance, which the power MOSFET has been unable to achieve, by providing a semiconductor layer having an opposite conductivity type to that of a source layer in a drain region, thereby producing conductivity modulation in the highly resistive drain layer to lower its ON resistance.
FIG. 25 is a longitudinal sectional view schematically showing the main portion of an n-channel type insulated gate bipolar transistor. The main portion is structured of a p.sup.+ type drain layer 1, n-type drain layer 2, gate oxide film 3, gate electrode 4, p type base layer 5, n.sup.+ type source layer 6, channel 7, interlayer insulating film 10, source electrode 14, and drain electrode 16.
When a voltage over a fixed threshold voltage with respect to the source electrode 14 is applied to the gate electrode 4, the surface of the p type base layer 5 under the gate electrode 4 is inverted to form the channel 7, through which electrons from the n.sup.+ type source layer 6 are allowed to flow into the n.sup.- type drain layer 2. The electrons flowing therein lower the potential of the n.sup.- type drain layer 2 and provides a forward bias to the p.sup.+ n.sup.- junction on the side toward the drain. As a result, holes as minority carriers flow from the p.sup.+ type drain layer 1 into the n.sup.- type drain layer 2. By the inflow of the holes, the n.sup.- type drain layer 2 is given conductivity modulation to greatly reduce its resistance value and becomes able to conduct a great amount of electric current.
However, as the current density increases within the element with the insulated gate bipolar transistor, a voltage drop due to the transverse resistance within the p type base layer 5 under the n.sup.+ type source layer 6 increases, whereby the junction between the n.sup.+ type source layer 6 and the p type base layer 5 is forward biased. Hence, electrons flow from the n.sup.+ type source layer 6 into the p type base layer 5, and as a result, a thyristor operation is casted due to a parasitic thyristor composed of the p.sup.+ type drain layer 1, n.sup.- type drain layer 2, p type base layer 5, and the n.sup.+ type source layer 6, that is, the so-called latch-up phenomenon occurs in which the current flowing through the semiconductor element becomes unable to turn OFF even if the gate-to-source bias is reduced to zero. Thus, the current amount controllable by the gate comes to be limited by the latch-up phenomenon (lowering of the latch-up current). The latch-up phenomenon occurs more easily when the element is turned OFF.
Further, the holes as the minority carriers injected into the n.sup.- type drain layer 2 in the insulated gate bipolar transistor remain accumulated in the n.sup.- type drain layer 2 even after the voltage applied to the gate electrode 4 has been reduced to zero and the flow of electrons in the channel 7 has been stopped, and the current continues to flow until the holes are flowed out through the source electrode 14 or the holes recombine with electrons to disappear. Thus, the turn-off time is prolonged. Accordingly, when the insulated gate bipolar transistor is used as a power switching element for motor control by a PWM (Pulse Width Modulation) system, for example, it becomes unable to increase the current switching frequency and the range of power control is thereby limited.
The latch-up phenomenon and increase in the turn-off time due to accumulated holes are more frequently occur at specific positions such as the border portion of the repeatedly disposed cells in the insulated gate bipolar transistor.
The reason for the above will be described below with reference to FIG. 26. FIG. 26 shows a sectional view of the structure in the vicinity of a gate bonding pad 15a as an example of the border portion of the cells.
As shown in FIG. 26, the cells are repeated at intervals of the pitch Wc and the current flowing into the source electrode 14 in a unit cell region 13 is determined by the carriers flowing through the n.sup.- type drain layer 2 (region 2a) with the width Wc. However, in the unit cell region (border portion cell) 12 adjoining the gate bonding pad 15a, the current flowing into the source electrode 14 is determined by the carriers flowing through the n.sup.- type drain layer 2 (region 2b) with the width Wc and WG, i.e., the current density in this cell becomes greater than that in the unit cell region 13 spaced from the gate bonding pad 15a. Accordingly, the voltage drop due to the current flowing through the p type base layer 5 of the unit cell region 12 adjoining the gate bonding pad 15a becomes greater than that in the unit cell region 13 spaced from the gate bonding pad 15a. Therefore, the latch-up phenomenon occurs more easily in the unit cell region 12 adjoining the gate bonding pad 15a and this causes the lowering of the latch-up current.
At the time when the element is turned off, since, in the region 11 and region 12 in FIG. 26, the minority carriers (holes) accumulated in the region 2b wider than the region 2a are flowed out into the source electrode 14 of the unit cell region 12, its switching speed becomes lower than that in the unit cell region 13 in which the minority carriers accumulated only in the region 2a are flowed out into the source electrode 14.
The above described phenomenon occurs not only in the vicinity of the gate bonding pad 15a but, as it is confirmed, at other border portion of the cells, as well, i.e., in the vicinity of the gate contact running region and the source bonding pad region.
Accordingly, a configuration for extracting the accumulated carriers into the source electrode 14 by making use of the border portion cell 12 adjoining the gate bonding pad 15a is disclosed, for example, in U.S. Pat. No. 4,631,564 or Japanese Laid-open Patent Publication No. 63-104480. The configuration is shown in FIG. 27.
As shown in FIG. 27, the p type base layer 5 for the border portion cell 12 shown in FIG. 26 is formed in contiguity with the p.sup.+ well layer (p type pad well layer) 8 provided under the gate bonding pad 15a for shielding the gate bonding pad 15a from the n.sup.- type drain layer 2, so that the holes accumulated under the pad are extracted via the p.sup.+ well layer 8 and through a contact hole formed by making use of the border portion cell 12 into the source electrode 14.
However, as to the design of the power switching element, it is lately desired to have the cell miniaturized so that a longer circumferential length of the channel may be obtained and as many cells as possible may be provided in the same chip area, thereby reducing the ON resistance still more and enhancing the capability of the power switching element to flow a large current, and also to have the cell miniaturized so that the element size may be decreased with the performance of the element remaining as it is.
To meet such demands, it is presumed that the cell will be miniaturized still more. However, a certain area is needed for the pad region in question to achieve wire bonding. Hence, the area for the pad region compared to the cell area has a tendency to increase as the cell becomes smaller in size. Consequently, with the conventional structure as shown in FIG. 27, the phenomenon of latch up easily occurs at the unit cell region (region 13) which newly becomes the border portion cell, and further, the turn-off time cannot be expected to be reduced so much.